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计算机系统应用英文版:2023,32(11):11-20
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RISC-V架构硬件辅助用户态内存安全防御方案概览
(1.中国科学院 信息工程研究所 信息安全国家重点实验室, 北京 100195;2.中国科学院大学 网络空间安全学院, 北京 101408)
Summary of Hardware-assisted User-mode Memory Safety Defenses on RISC-V Architechture
(1.State Key Laboratory of Information Security, Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100195, China;2.School of Cyber Security, University of Chinese Academy of Sciences, Beijing 101408, China)
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Received:May 26, 2023    Revised:June 27, 2023
中文摘要: 传统的用户态内存安全防御机制基于x86架构和纯软件方式实现, 实现内存安全保护的运行时开销很高, 难以部署在生产环境中. 近年来, 随着主流商业处理器开始提供硬件安全扩展, 以及RISC-V等开源处理器架构的兴起, 内存安全保护方案开始面向x86-64、ARM、RISC-V等多种体系架构和硬件辅助实现方式. 我们对RISC-V架构上实现的内存安全防御方案进行了讨论, 并对x86-64、ARM、RISC-V等处理器架构在安全方案设计上的特点进行了比较. 得益于开放的指令集架构生态, RISC-V架构的内存安全防御方案相较于其他架构有一些优势. 一些低成本的安全防御技术有望在RISC-V架构上实现.
中文关键词: RISC-V  内存安全  硬件安全扩展  处理器
Abstract:Traditional x86-based and software-based user-mode memory safety defenses can hardly be deployed in a production-ready environment due to significant runtime overheads. In recent years, as mainstream commercial processors begin to provide hardware security extensions and open-source architectures like RISC-V rise, hardware-assisted memory safety protections have become popular, and their implementations are based on various architectures, such as x86-64, ARM, and RISC-V. This study discusses user-mode memory safety defenses on the RISC-V architecture and compares the features of x86-64, ARM, and RISC-V in the context of security defense design. RISC-V has some advantages over other architectures due to its opening ecosystem, making the implementation of some low-cost and promising defense techniques possible.
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基金项目:国家自然科学基金(61802402, 62172406); 中国科学院率先行动“百人计划”青年俊才(C类)
引用文本:
解达,欧阳慈俨,宋威.RISC-V架构硬件辅助用户态内存安全防御方案概览.计算机系统应用,2023,32(11):11-20
XIE Da,OUYANG Ci-Yan,SONG Wei.Summary of Hardware-assisted User-mode Memory Safety Defenses on RISC-V Architechture.COMPUTER SYSTEMS APPLICATIONS,2023,32(11):11-20