Abstract:Phase Change Memory (PCM) has become a candidate of future main memories due to its attractive characteristics of non-volatility, high access speed, and low power consumption. Meanwhile, how to efficiently integrate PCM into current memory systems is becoming a hot topic. Generally, there are a number of choices to use PCM as main memory, e.g., to construct PCM-only main memory systems, or to construct DRAM/PCM-based hybrid memory systems. However, the conflict between numerous PCM-related researches and lack of real devices hinders evaluations of PCM-aware algorithms. Therefore, in this paper, we propose a DRAM/PCM-based hybrid memory simulator. The new features of the simulator are manifold. First, it can simulate different DRAM/PCM-based memory systems, including the hierarchical architecture (DRAM as the cache of PCM) and the hybrid architecture (both DRAM and PCM as main memory). Second, it leverages a clock-accurate timing model to emulate accesses on PCM. Third, it offers a hybrid memory allocation interface that can be easily used by programmers. After a description of the simulator framework, we present basic evaluation results and a case study of the simulator, which suggest its feasibility.