Abstract:The development of image real-time processing system has brought a good platform of the widespread use of FPGA. Aiming at the problem that traditional median filter algorithm cannot process collected images quickly and efficiently, this paper adopts improved median filter and makes use of advantages, such as fast running speed, parallel running of inner program, to design an image preprocessing system with high real time ability and high flexibility. Using the features of median filter and Verilog hardware description language to code. And then realize simulation in Quartus II and Modelsim. At last, compared with MATLAB median filter simulation figure and multilevel median filter, it has shown that using FPGA to process and improve median filter can not only conduct median filter to images successfully, but also has the ability of fast operation speed and low energy consumption.