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Received:June 11, 2011 Revised:July 11, 2011
Received:June 11, 2011 Revised:July 11, 2011
中文摘要: 随着网络带宽的快速增长,正则表达式匹配逐渐成为网络数据处理系统的性能瓶颈。为了获得更高的匹配效率,基于FPGA 的正则表达式匹配引擎成为近年来的研究热点之一,而将正则表达式高效的转换成硬件描述语言是其中的关键技术。首先分析了正则表达式转换为硬件电路的算法,然后在此算法基础上实现了一个编译器。最后在Modelsim 平台上进行了仿真,仿真结果证明了编译器的正确性。
Abstract:With the rapid development of network bandwidth, regular expression matching is becoming the performance bottleneck of networking data processing system. For the purpose of achieving higher matching speed, regular expression matching engine based on FPGA has become one of the recent hot fields. And it is the critical technology how to efficiently transfer regular expression to hardware description language. In this paper, we first analyze the algorithm of converting regular expression to hardware circuit, and then implement a compiler based on this algorithm. Finally we simulate the circuit on the Modelsim platform. The results proved the accuracy of the compiler.
keywords: regular expression FPGA pattern matching Verilog
文章编号： 中图分类号： 文献标志码：
基金项目:
| Author Name | Affiliation |
| DENG Kai-Yuan | School of Photoelectric Information and Communication Engineering, Beijing Information Science and Technology University, Beijing 100101, China |
| Author Name | Affiliation |
| DENG Kai-Yuan | School of Photoelectric Information and Communication Engineering, Beijing Information Science and Technology University, Beijing 100101, China |
引用文本：
邓凯元.基于Verilog 的正则表达式编译器的实现.计算机系统应用,2012,21(2):229-232
DENG Kai-Yuan.Implementation of Regular Expression Compiler Based on Verilog.COMPUTER SYSTEMS APPLICATIONS,2012,21(2):229-232
邓凯元.基于Verilog 的正则表达式编译器的实现.计算机系统应用,2012,21(2):229-232
DENG Kai-Yuan.Implementation of Regular Expression Compiler Based on Verilog.COMPUTER SYSTEMS APPLICATIONS,2012,21(2):229-232
