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Received:December 18, 2010 Revised:March 07, 2011
Received:December 18, 2010 Revised:March 07, 2011
中文摘要: 通过分析3*3 窗口滤波的数学模型,以FPGA 为平台,使用VHDL 硬件描述语言设计,实现中值滤波图像处理算法.在设计过程中,通过改进的中值滤波算法和优化结构,在合理利用硬件资源的基础上,有效地运用算法内在的并行性,同时采用流水线结构优化改进算法,提高了处理速度.
Abstract:Through the analysis of the mathematical model of 3*3 template based on FPGA platform, this paper uses VHDL hardware description language to design and implement median filtering algorithm. In the design, through improved algorithms and optimizing the structure, the rational use of hardware resources is made, with the internal parallelism in the algorithm effectively used. At the same time, the pipelining uses structural optimization algorithm and improves the processing speed.
keywords: FPGA median filtering pipelining
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引用文本：
李新春,赵璐.基于中值滤波算法滤波器的FPGA 实现.计算机系统应用,2011,20(9):82-85,72
LI Xin-Chun,ZHAO Lu.Implementation of FPGA Based on Median Filtering Algorithms Filter.COMPUTER SYSTEMS APPLICATIONS,2011,20(9):82-85,72
李新春,赵璐.基于中值滤波算法滤波器的FPGA 实现.计算机系统应用,2011,20(9):82-85,72
LI Xin-Chun,ZHAO Lu.Implementation of FPGA Based on Median Filtering Algorithms Filter.COMPUTER SYSTEMS APPLICATIONS,2011,20(9):82-85,72
