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Received:January 17, 2010 Revised:March 20, 2010
Received:January 17, 2010 Revised:March 20, 2010
中文摘要: 为了实现图像的实时处理，常采用现场可编程门阵列FPGA对采集到的图像数据进行预处理。以对Micron MT9V112传感器的Bayer图像数据处理为例，首先就Bayer 数据坏点修正、Bayer转RGB888及RGB888降噪进行了介绍，然后应用Verilog HDL语言设计出相应的硬件模块，最后结合MATLAB对硬件模块处理后的数据做了相应的测试。仿真结果表明，硬件模块对640x480数据的处理满足系统实时性要求。
中文关键词: 图像预处理单元 Verilog HDL 现场可编程门阵列
Abstract:During the procedure of real–time image processing, FPGA is often utilized to preprocess the collected digital image. This project looks at how to process the Bayerdata, which comes from Micron MT9V112-1/6-Inch SOC VGA CMOS DIGITAL IMAGE SENSOR. The study first introduces the bad pixel correction of Bayerdata, the procedures of converting an image from the Bayer format, to an RGB888 format and RGB888 images denoising methods. The paper then examines the data from an image preprocessing module based on Verilog HDL via Matlab. The discovery demonstrates that this module can successfully process 640x480 pixels with desirable real-time results.
keywords: image preprocessing unit Verilog HDL FPGA
文章编号： 中图分类号： 文献标志码：
基金项目:湖南省科技计划(2009GK3082)
| Author Name | Affiliation |
| ZHU Xi | 湖南大学 电气与信息工程学院 湖南 长沙 410082 |
| WANG Ling | |
| ZHENG Shan-Xian | |
| GUO Xiang-Yong |
| Author Name | Affiliation |
| ZHU Xi | 湖南大学 电气与信息工程学院 湖南 长沙 410082 |
| WANG Ling | |
| ZHENG Shan-Xian | |
| GUO Xiang-Yong |
引用文本：
朱喜,王玲,郑善贤,郭湘勇.基于FPGA的图像预处理单元的硬件实现.计算机系统应用,2010,19(10):68-70
ZHU Xi,WANG Ling,ZHENG Shan-Xian,GUO Xiang-Yong.Hardware Implementation of PPU Based on FPGA.COMPUTER SYSTEMS APPLICATIONS,2010,19(10):68-70
朱喜,王玲,郑善贤,郭湘勇.基于FPGA的图像预处理单元的硬件实现.计算机系统应用,2010,19(10):68-70
ZHU Xi,WANG Ling,ZHENG Shan-Xian,GUO Xiang-Yong.Hardware Implementation of PPU Based on FPGA.COMPUTER SYSTEMS APPLICATIONS,2010,19(10):68-70
