Memory safety is critical but vulnerable. In view of this, numerous defense countermeasures have been proposed, but few of them could be applied in a production-ready environment due to unbearable performance overhead. Recently, as open-sourced architectures like RISC-V emerge, the extension design of enhancing hardware memory safety has revived. The performance overhead of hardware-enhanced defense techniques becomes affordable. To support the extension design of enhancing memory safety systematically, this study proposes a comprehensive and portable test framework for measuring the memory safety of a processor. In addition, the study achieves an open-sourced initial test suite with 160 test cases covering spatial and temporal safety of the memory, access control, pointer and control flow integrity. Furthermore, the test suite has been applied in several platforms with x86-64 or RISC-V64 architecture processors.