With the development of ASIC, SoC and FPGA in research and industry, Verilog HDL has been the main method to design the integrate circuit. For the designer miusing the assignments in Verilog HDL, more and more designs have been with some invisible bugs. That the designers fully understand how the assignments are scheduled in the program has been the main method to solve the bugs. This paper is based on the stratified event queue to detail how the assignment works in design, and gives important coding guidelines to infer correct logic and avoid race condition in the design.