A coprocessor specially applied for encryption and decryption flow control was designed. According to the specific application requirement, a kind of reduced 8-bit width instruction set was designed with 32-bit data width design compliant to SoC system. The coprocessor adopted 3 stage pipeline design with data bypass design to prevent data hazards. Joint test with secure IPs showed that the coprocessor could control the encryption and decryption flow flexibly. Experiments on SM1 encryption proved that the coprocessor could provide better performance than the main processor and release main processor resources. The Design Compiler synthesis result showed the coprocessor occupied only a small area.