Design and Implementation of Dual-FPGA High-Speed Digital System
DOI:
CSTR:
Author:
Affiliation:

Clc Number:

Fund Project:

  • Article
  • |
  • Figures
  • |
  • Metrics
  • |
  • Reference
  • |
  • Related
  • |
  • Cited by
  • |
  • Materials
  • |
  • Comments
    Abstract:

    Centering on two pieces of Spartan-3E series FPGA chip XC3S500E,the system uses ADC MAX12529 for high-speed synchronous sampling and DAC902 for real-time signal generating. Two pieces of FPGA can communicate with each other by interconnecting the 8-bit GPIO, or by the sharing of high-speed dual-port RAM. Its configuration circuits are independent, and it constitutes a high-performance digital system with a FLASH memory, respectively.

    Reference
    Related
    Cited by
Get Citation

罗旗舞,谢洪途,黎福海.双FPGA高速数字系统的设计与实现.计算机系统应用,2010,19(10):135-138

Copy
Share
Article Metrics
  • Abstract:
  • PDF:
  • HTML:
  • Cited by:
History
  • Received:January 26,2010
  • Revised:March 18,2010
  • Adopted:
  • Online:
  • Published:
Article QR Code
You are the firstVisitors
Copyright: Institute of Software, Chinese Academy of Sciences Beijing ICP No. 05046678-3
Address:4# South Fourth Street, Zhongguancun,Haidian, Beijing,Postal Code:100190
Phone:010-62661041 Fax: Email:csa (a) iscas.ac.cn
Technical Support:Beijing Qinyun Technology Development Co., Ltd.

Beijing Public Network Security No. 11040202500063