FPGA Low Power Design Using Pipeline
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    Abstract:

    By adding new registers in combinational logic, pipeline can reduce the generation and propagation of glitch. This paper compares the power dissipation of pipeline design and non-pipeline design, using low transition probability signals, random transition probability signals and high transition probability signals. It comes to the conclusion that pipeline can reduce power dissipation in high transition probability signals design, but for low transition probability signals design, pipeline may consume more power, and its reason is analyzed.

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李宏钧,胡小龙.流水线的FPGA低功耗设计①.计算机系统应用,2010,19(8):234-237

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  • Received:December 13,2009
  • Revised:January 07,2010
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