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一种分解演化的电路自动设计方法①
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国家自然科学基金(60773009);国家高技术研究发展计划(863)(2007AA01Z290)


Automated Circuit Design Methodology Using Decomposition Evolution
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    摘要:

    提出一种并行递归分解算法，它有规律地将待演化电路逐步分解直到设计成功，整个过程无需人工干预，提高了电路设计的自动化程度。该算法将目标电路的演化设计过程转化为其多个子电路的并行演化过程，并利用“特长个体”的互补性提高搜索效率。实验表明，该分解策略能有效提高演化逻辑电路的设计效率和成功率。

    Abstract:

    A Parallel and Recursive Decomposition algorithm is proposed. It divides the system into some simple ones regularly until the function is achieved. This decomposition process consequently dispense with human interference. The proposed algorithm regards the sought circuits as many parallel evolving subcomponents and utilizes the complementary of "elitists" during evolution to guide decomposition process. The experimental results show that it greatly enhances the efficiency and hit effort of evolving digital logic circuits.

    参考文献
    1 Stoica A, Keymeulen D, Zebulum RS, Ferguson MI. On Two New Trends in Evolvable Hardware: Employment of HDL-based Structuring, and Design of Multi-functional Circuits. Proc. of the 2002 NASA/DOD Conference on Evolvable Hardware (EH 02),IEEE.56－59.
    2 赵曙光,杨万海.基于函数级FPGA原型的硬件内部进化.计算机学报, 2002,14(8):666－669.
    3 何国良,李元香,涂航,张伟,张大斌.演化硬件平台的数字电路仿真算法.系统仿真学报，2006,18(9): 2661－2664
    4 赵曙光,王宇平,杨万海,焦李成.基于多目标自适应遗传算法的逻辑电路门级进化方法.计算机辅助设计与图形学学报, 2004,16(4):402－406
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    6 Bidlo M. Evolutionary Design of Generic Com- binational Multipliers Using Development. Proc. of 7th International Conference on Evolvable Systems:From Biology to Hardware, 2007, Springer-Verlag. 77－78.
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    9 Torresen J. Evolving multiplier circuits by training set and training vector partitioning. Proc. of Fifth Int. Conf. on Evolvable Hardware (ICES),2003,Springer. 228－237.
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朱继祥,李元香.一种分解演化的电路自动设计方法①.计算机系统应用,2010,19(8):52-56

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  • 收稿日期:2009-11-16
  • 最后修改日期:2009-12-22
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