Dynamic binary translation (DBT) is an efficient technology for instruction set simulation, commonly used to build CPU simulation models. However, significant challenges arise when simulating digital signal processors (DSP). High-performance DSP, such as TI’s TMS320C6X series, often adopt very long instruction word (VLIW) architectures and include specialized hardware and instructions to simplify the use of software-pipelined loops. The absence of explicit conditional branch instructions and loop counter modification operations in such loops, along with the reordering, overlapping, and masking of instructions within the loops, makes translating these loops using DBT technology highly challenging. To address this, this study proposes a novel dynamic translation approach. The approach involves serializing parallel loop iterations, generating translation blocks for different states, and overlapping the instructions of inner and outer loops while aligning them by cycle to synchronize the translation of outer and inner loops, thereby accurately simulating the execution of software-pipelined loops. Experimental results show that when running commonly used code containing software pipelining (e.g. dsplib), the proposed simulator employing this translation approach produces results identical to those from a hardware development board, demonstrating the correctness of the solution. Moreover, the proposed simulator performs 3.25× faster than TI’s official simulator.