Traditional x86-based and software-based user-mode memory safety defenses can hardly be deployed in a production-ready environment due to significant runtime overheads. In recent years, as mainstream commercial processors begin to provide hardware security extensions and open-source architectures like RISC-V rise, hardware-assisted memory safety protections have become popular, and their implementations are based on various architectures, such as x86-64, ARM, and RISC-V. This study discusses user-mode memory safety defenses on the RISC-V architecture and compares the features of x86-64, ARM, and RISC-V in the context of security defense design. RISC-V has some advantages over other architectures due to its opening ecosystem, making the implementation of some low-cost and promising defense techniques possible.