In this study, we design and implement an automatic testing system for semantic equivalence of RISC-V assembly programs. While developing RISC-V programs, especially developing efficient programs based on extension instructions (such as vector extension), developers often write assembly code manually. For example, for the standard C function library, we often write the corresponding vector version functions for better performance. Without the compiler, the manually developed assembly code can maximize the efficiency of the program, but it skips many important compilation processes (such as type checking and register allocation), thus putting forward higher requirements for the developers. It will greatly affect the correctness of the code and the efficiency of software development and debugging if we can quickly and automatically test whether the rewritten version is semantically equivalent to the standard version of the program. The existing RISC-V testing framework lacks support for semantic equivalence testing and fails to consider the side effects caused by program executions. Based on the dynamic test environment of a simulator, this research designs and implements an automatic testing system for semantic equivalence of RISC-V assembly programs. It can capture side effects caused by program executions through monitoring machine states and generate testing reports with user-defined testing targets. Experiments show that the system, compared with existing testing systems, can test the semantic equivalence of RISC-V assembly programs.