The pipeline is the key technology of manufacturing high-performance CPU. The OR1200, which has been widely studied currently, is a 4-stage pipeline CPU with a free open source. Without MEM stage which should be designed in OR1200, the pipeline will be stalled to wait for load or store instruction. In this research, we design a MEM stage for OR1200 in LSU. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. On the other hand, when a data requested by a load instruction has not yet become available, it leads to load-use hazards. To resolve this hazard problem, we design a data valid signal Tag to control stalling of pipeline. The pipeline is stalled by the Tag signal for one stage and then continues with the forwarding of data, as the simulation result shows.