Software-based hash function has been popularly applied to current networking searching area, but it is difficult to meet the demand of high-speed real-time applications in backbone network and services with mass data. In the general design of hardware-based hash function, there are still some drawbacks such as complex logic circuit memory inefficiency, and incremental updates for dataset needed to be solved. This paper proposed a design of hardware perfect hash function on FPGA based on bit-extraction algorithm, using simple bit-selection and bit logic operation. The achievable load factor can be up to 1, and the amortized memory cost of the hash function is about 2.8-5.6 bits/key for 32-bit keys, and the system clock frequency is about 300MHz(Throughput more than 14Gbps). The proposed method can be applied to real-time applications that require high-speed table lookup, e.g. IP address lookup, packet classification, string matching and intrusion detection systems.