More and more people pay attention to real-time three-dimensional dynamic display technology based on computer generated hologram. The major problem to restrict its development is computing speed. To solve the problem, we build PC-FPGA distributed computing holographic hardware acceleration system that multi-chip FPGA hardware block computing paralleled. Each chip FPGA unit must have the functions both of holographic algorithms computing and the data transmission to achieve this goal. Therefore, NIOS II soft core transplant uC/OS II operating system and LWIP Ethernet protocol stack based on already CGH algorithm acceleration module, NIOS II as the MCU to control CGH algorithm acceleration module and Ethernet data transmission. The article will introduce the NIOS II soft-core, uC/OS II and LWIP achieve to Ethernet data transmission process. To provide a new method to the realization of three-dimensional dynamic real-time display based on CGH.