To address the demand for bandwidth isolation in high-throughput network environments, this study proposes a high-precision bandwidth limiting technique based on FPGA, which implements a hardware token bucket mechanism. A novel time-driven model converts the traditional cycle-accumulating token bucket into a transmission-time computation mechanism, thereby avoiding the overhead caused by per-cycle token updates. In addition, an integer-equivalent token injection technique is introduced to eliminate floating-point operations while enabling fine-grained rate control over a wide range from 10 Mb/s to 100 Gb/s. The system adopts a pipelined architecture and dual-port BRAM optimization, supporting parallel rate-limiting scheduling for over 4k queues. Experiments on the Xilinx Alveo U200 platform demonstrate that, in single-queue scheduling scenarios, the proposed technique achieves nearly 100% throughput improvement, with substantial reductions in resource usage (an 89% reduction in LUT, 77% in registers, and ≥20% in BRAM). The rate control error remains below 0.1%. This technique provides a nanosecond-precision and highly scalable bandwidth isolation solution for high-performance network systems.