Wafer-level chips, with their enhanced integration density, superior interconnect characteristics, and lower power consumption, represent a pivotal future technology in the integrated circuit field during the post-Moore era. However, conventional simulation methods suffer from low efficiency, a lack of cross-chiplet communication modeling, and inadequate handling of heterogeneous computing resources when applied to wafer-level chips. To address the simulation requirements for wafer-level chip architectures, this study proposes a parallel discrete simulation method based on the coordination of operators and chiplets. By leveraging the coordinated parallel discrete simulation of operators and chiplets, the method effectively enhances the simulation efficiency of the system. First, a foundational standardized chiplet library and an operator library are constructed to support the architecture simulation. Subsequently, complex computation tasks are decomposed into multiple operators using the operator library, and parallel discrete simulation is realized through the collaboration of multiple cores. Communication models are incorporated to ensure the accuracy of the system simulation results. Experimental results demonstrate that compared to conventional simulation methods based on SST and Gem5, the proposed approach not only supports simulation modeling of communication between heterogeneous chiplets but also achieves an average speedup of over 4.8 times with an average accuracy loss of less than 1.3%, significantly improving the simulation efficiency for wafer-level chip systems.