Abstract:CRC codes are widely used in networking and storage, and many other occasions due to its simple encoding rules. With the development of modern storage and transmission technologies, the check of software code has been difficult to meet the needs of high level transmission of Gbit. This paper has been achieved highly parallel cyclic redundancy check (CRC) system which based on FPGA technology to design a multi-channel high-speed technology. The design uses five parallel channels of 2Gbps check in order to achieve data throughput rate of 10Gbps. Each CRC channel compatible with 32-bit Ethernet standard. This design uses VerilogHDL for hardware description language, QuartusII8.0 for Integrated wiring, and packaging the processing unit into an independent IP core, then uses the Altera Corporation’s EP2C20F484C6 chips as download target for verification. The results show that the design can meet the rate’s requirements of high-speed data integrity checks.