Network Intrusion Prevention System (NIPS) is one of the effective tools in providing network security. The core computing function of an NIPS is Pattern Matching Engine (PME), which is used to search pattern data of a known network intrusion from network packages. In current NIPS, PME consumes a significant portion of the computing time. PME is a computing consuming application, requiring high level performance from the system’s base computing power. This article proposes a parallel pattern matching approach and maps the computation onto the existing multi-core CPU by fully utilizing the computing power of the base hardware structure of the prevention system. The implementation of the proposed approach on IBM System x3455 server shows that it provides a typical processing speed of 17.2 Gbps with a capacity of 50,000 pattern signatures, which has exceeded the results of all current documentation, including FPGA, ASIC, network CPU, and GPU.